[Device] Family = lc4k; PartNumber = LC4064ZC-37M56C; Package = 56csBGA; PartType = LC4064ZC; Speed = -3.7; Operating_condition = COM; Status = Production; [Revision] Parent = lc4k64c.lci; DATE = 03/09/2006; TIME = 14:35:54; Source_Format = ABEL_Schematic; Synthesis = Exemplar; [Ignore Assignments] [Clear Assignments] [Backannotate Assignments] [Global Constraints] [Location Assignments] layer = OFF; CK = pin, K8, -, -, -; RCK = pin, A5, -, -, -; RCKO = pin, A4, -, -, -; FCK = pin, H6, -, -, -; FCKO = pin, H5, -, -, -; TCK = pin, K6, -, -, -; TCKO = pin, K7, -, -, -; ECK = pin, C5, -, -, -; ECKO = pin, C6, -, -, -; RELAY = pin, D8, -, -, -; F0 = pin, A3, -, -, -; F1 = pin, A2, -, -, -; F2 = pin, A1, -, -, -; F3 = pin, C1, -, -, -; F4 = pin, D1, -, -, -; SHDN = pin, H7, -, -, -; TP1 = pin, H1, -, -, -; TP2 = pin, F1, -, -, -; TP3 = pin, G1, -, -, -; CONV = pin, C10, -, -, -; SDI = pin, D10, -, -, -; SDO = pin, E10, -, -, -; SCK = pin, G10, -, -, -; [Group Assignments] layer = OFF; [Resource Reservations] layer = OFF; [Fitter Report Format] [Power] [Source Constraint Option] [Fast Bypass] [OSM Bypass] [Input Registers] [Netlist/Delay Format] [IO Types] layer = OFF; [Pullup] Default = HOLD; [Slewrate] [Region] [Timing Constraints] [HSI Attributes] [Input Delay] [opt global constraints list] [Explorer User Settings] [Pin attributes list] [global constraints list] [Global Constraints Process Update] [pin lock limitation] [LOCATION ASSIGNMENTS LIST] [RESOURCE RESERVATIONS LIST] [individual constraints list] [Attributes list setting] [Timing Analyzer] [PLL Assignments] layer = OFF; [Dual Function Macrocell] [Explorer Results] [VHDL synplify constraints] [VHDL spectrum constraints] [verilog synplify constraints] [verilog spectrum constraints] [VHDL synplify constraints list] [VHDL spectrum constraints list] [verilog synplify constraints list] [verilog spectrum constraints list] [verilog synplify constraints.Verilog Standard V2001.Alias] [Register Powerup] [Constraint Version] version = 1.0; [Node attribute] layer = OFF; [SYMBOL/MODULE attribute] layer = OFF; [Nodal Constraints] layer = OFF;