DFPS Fiber Controller (A3045)

© 2022 Kevan Hashemi, Open Source Instruments Inc.

Contents

Description
Versions
Design
Development

Description

[26-AUG-22] The Direct Fiber Positioning System (DFPS) Controller (A3045) is a rectangular circuit that generates the control voltages for a single two-axis fiber positioner. The board takes as input ±250 V, 0 V, and 3.3 V power supplies and two single-ended 3.3-V logic levels Serial Clock (SCK) and Serial Data In (SDI). For outputs it has ±250-V control voltages North (VN), South (VS), East (VE), and West (VW) as well as a single-ended 3.3-V logic level Serial Data Out (SDO). The A3045 is designed to plug into a service board such as the DFPS Base and Service Board (A3043).


Figure: Fiber Controller (A3045A). Top: Bottom side with P0402 resistors, capacitors, and fuses. Bottom: Top side with connector, logic chip (U1), transistors and larger capacitors. Length 56.0 mm, width 8.7 mm, height 1.9 mm away from connector.

The A3043A controller could, in principle, be deployed in a fiber positioning system of any size. Our prototype design deploys sixteen A3045As in a 4×4 array, as shown below.


Figure: Sixteen Controller Boards Mounted to Service Board, Side View.

Each controller holds four high-voltage amplifiers with gain ×200 and output range ±250 V. These are driven by four slow digital to analog converters (DACs) with 0.1% precision. The DACs are driven by the controller logic, which communicates with the backplane through the service board over a two-wire bus. The controllers are identical assemblies except for their identification numbers, which allow them to be selected individually over the backplane.


Figure: Three 4×4 Positioner Cells On Bridge with Frame. The controllers are shown 30-mm long, but they will in fact be 60-mm long.

The DACs perform their digital to analog conversion by low-pass filtering a square wave of variable duty cycle. Thus each DAC consists of a counter, a logic output, and a low-pass filter. Aside from the DACs, the A3045's logic chip is host to an OSR8 microprocessor and a serial command receiver.

Versions

The following versions of the DFPS Fiber Controller (A3045) are defined.

Version Service Board Geometry Comment
A A3043 9 mm wide, 60 mm long, Single-fiber controller with 12-way connector.
Table: Versions of the DFPS Fiber Controller (A3045).

Design

S3045A_1.gif: Fiber Controller Service Interface, schematic for A3045A.
S3045A_2.gif: Fiber Controller DACs and Amps, schematic for A3045A.
A304501A.zip: Geber files for A3045A PCB.
A304501A_Top.svg: View of top side of A304501A.
A304501A_Bottom.svg: View of bottom side of A304501A.
A3045AV1_Top.gif: Top-side component map of A3045AV1.
A3045AV1_Bottom.gif: Bottom-side component map of A3045AV1.
A78554.pdf: Twelve-way, female, dual-row, right-angle, connector for controllers.
A78557.pdf: Twelve-way, male, dual-row, vertical, connector for service boards.
A3045A_Drawing.gif: Drawing of A3045A and connectors.
A3045A_Side.gif: Side view of sixteen A3045A mounted to service board.
A3043A_Bottom.gif: Drawing of sixteen A3045A mounted to service board, with dimensions.
P3045: Firmware and software repository.

Development

[04-MAY-22] We arrange components on the A304501A printed circuit board: four high-voltage amplifiers, logic, and oscillator. We have plenty of space with a 60-mm long, 9-mm wide board, provided we can place P0402 resistors on the bottom side. These resistors are 0.35 mm high. We drop the board thickness to 0.53 mm (0.021"). We plan to stiffen the boards with an epoxy coating, and we will try to mount capacitors perpendicular to the board length so they do not crack when the board flexes during assembly. Our SOT-23 transistors are 1.1 mm high. In our arrangement on the service board, we have 2.6 mm between the top sides of A3043A boards, and we need 2.2 mm for two sets of SOT-23 transistors, so we have 0.4 mm clearance. The bottom sides of neighboring controller boards are separated by 1.1 mm. We need 2 × 0.35 mm = 0.7 mm for two sets of P0402 resistors or low-profile capacitors. We have 0.4 mm clearance.

[18-JUL-22] There is a third region on the circuit board: beside the connector on the top side. In this region, we have 0.8 mm clearance to the connector on the neighboring controller. We can place P0402 resistors here on top and bottom side.

[27-JUL-22] We are trying to choose the oscillator for the A2045A. The SiT1579 is a remarkable device: at 1 MHz it consumes less than 20 μA. But its package is a ceramic BGA-4 that has given us a lot of trouble in the past, when we used it on implantable transmitters. For a long time we had this device hand-placed to avoid cracking it, because it would otherwise fail more than half the time during assembly. We also had them fail by corrosion during implantation even when hand-placed. As we discussed earlier, we can make do with a 200 kHz clock on the A2045A to drive duty-cycle, ten-bit DAC. Although 200 kHz oscillators with sufficiently low current consumption do exist, they are not available for purchase during this semiconductor shortage, nor will they be available for months.

[29-JUL-22] To the first approximation, a 1% change in our low-voltage power supplies will result in a 1% change in our electrode voltages. If we want our fiber tip to be stable to 10 μm in a 3.8-mm range, the power supply must be stable to better than 0.3%. We resolve to generate on the backplane 0.01% stable 2.50 V and 1.25 V power supplies that we will distribute to all controllers. These power supplies will be fused on the controller with a 50-mA fuse. We will run the controller's OSR8 processor off a 32.768 kHz micropower oscillator, and we will run continuously a ring oscillator in the logic that will consume 1 mA from 1.25 V, which is 1.25 mW. We divide down the ring oscillator to roughly 1 MHz to duty our duty-cycle DAC. One gate switching at 1 MHz consumes roughly 10 μA, and we are going to implement four 12-bit DACs, so we expect another 240 μA to flow to the DACs. We hope to limit the low-voltage power consumption to 2 mW.

[01-AUG-22] We complete the design of the A3045AV1 circuit. We have elminated the two regulators and the high-frequency oscillator, leaving a 32.768 kHz oscillator to act as timing for incoming and outgoing communication. This communication will use the same protocol as our implantable stimulators. It is one-wire each direction, and the wire can be shared among any number of receivers. We route one of the amplifiers with its duty-cycle DAC in a 10.0 mm × 8.3 mm area. Our A304501A layout is 56 mm × 8.6 mm (2.20 in × 0.34 in), slightly smaller than the 60.0 mm × 9.0 mm permitted by our drawings, allowing us 0.2 mm thickness of epoxy on the long edges. We must cover the circuit board with something non-conducting and tough or else we will not be able to pack them next to one another without a risk of shorting the power supplies. We are using five layers, 5-mil tracks, and 8-mil via holes. Assuming four FR4 layers of equal thickness, and finished thickness 21 mil, each layer of FR4 will be around 125 μm. The breakdown voltage of FR4 is 20 kV/mm, so we don't expect breakdown between layers until around 2.7 kV and we have at most 0.5 kV between layers.

[03-AUG-22] We are able to run all connections to the WLCSP-25 along the top layer, provided we can run diagonal tracks between the pads. The balls are on a 16-mil pitch. With 5-mil tracks we have 4-mil clearance between the diagonal tracks and the edges of the balls.


Figure: Proposed Top-Layer Only Routing of Logic Chip Connections.

By using only the top layer, we avoid needing microvias from the pads to the middle copper, which will speed up production of the board and reduce its cost.

[08-AUG-22] Fiber controller printed circuit boards are on their way, A3045 with solder paste stencil.

[24-AUG-22] We have our A304501AR1 printed circuit boards as well as a stencil. We apply paste with the stencil and load the three components that are most difficult to load by hand: J1, U1, and U2. So far as we can tell, J1 is impossible to load by hand. In the oven, J1 and U2 reflow perfectly. But we see balls under U1, the 0.4-mm pitch WLCSP-25, are joined. We remove U1 and load another by hand, using a solder blob on the top side, a 650F iron, and 20 s. We load C3 and C4. We connect 2V5 and 1V2 to 1.2V with 0.7-mm diameter SCT leads. These leads are stainless steel coils insulated with silicone.


Figure: First Parts Loaded onto A3045AV1. Note programming socket P1.

Our task now is to program the logic chip through the SIP1MM-8. We construct an adaptor for the 1-mm pitch plug using our 0.7-mm diameter SCT leads.


Figure: Programming Cable Adaptor. On the left is a 0.1" pitch plug that mates with our programming cable. On the right is a 1-mm pitch plug that we press into the P1 socket on the A3045.

With our adaptor and 1.2 V applied to both power supplies, we are able to scan U1 correctly, but we cannot program the chip. The resistance of our SCT leads is 6 Ω/cm. Our power supply leads are each 40 mm long, so we have roughly 50 Ω in series with our 1.2-V power supply. During programming, current gets as high as 20 mA, which will drop 1 V with our leads, so programming is impossible.

[25-AUG-22] We reduce the length of our 1.2-V supply lead to 1 cm and connect 0V directly to the PCB's ground pad. We are still unable to program the logic chip, we get an "OTP bit set" error. Replace the chip. Get same error. Check programming cable with an A3041A and it works fine. Go back to A3045. Forget to turn down power supply from 2.7 V to 1.2 V. We check "Progam Pin Connecte" in the programming software. We are able to program the chip. We notice our power supply error half-way through. Supply 2.5 V to 2V5 and 1.2 V to 1V2 and see 77 μA on 1V2 and 220 μA on 2V5. We try to re-program with these power supplies and get the same "OTP bit set" error. Increase 1V2 to 2V3 and all goes well. We remove our 1V2 and 2V5 supply leads. Their resistance is 7 Ω and 11 Ω respectively.

[26-AUG-22] We use copper wire to deliver 1V2 and 2V5. Our programming cable adaptor leads are 25 mm long. Resistance is roughly 15 Ω each. We can scan and erase the logic chip with 1.2 V and 2.5 V applied to 1V2 and 2V5 respectively. We try applying 2.5 V to both 1V2 and 2V5. Scan and erase succeed but programming fails. We drop 2V5 to 2.0 V. Scan, erase, and programming all succeed. We restore 2V5 to 2.5 V. We have 69 μA flowing into 1V2 and 250 μA flowing into 2V5. This turns out to be because TP4=2V5 and we have current flowing through R4. Reprogram and 1V2 current is 69 μA while 2V5 current is 2.5 μA for 2V5 = 1.2 V and 4.5 μA for 2V5 = 2.5 V. We get the CPU running and enable the ring oscillator. We have 489 μA flowing into 1V2.

Firmware P3045 V1.2 has ND, SD, ED, and WD provided by variable-resolution duty-cycle digital to analog converters (DACs). Software sets a two-byte value for each electrode output. We have our ring oscillator running and from it we derive Digital to Analog Converter Clock (DCK), nominally 10 MHz, as set by fck_divisor in ROM.asm. With fck_divisor = 8 we measure DCK = 10.9 MHz. A counter running on DCK counts from 0-65535 in steps of dac_step, also set by ROM.asm. With dck_divisor = 1 we measure 166 Hz. With dac_step = 8 we measure 1.2 kHz. With dac_step = 1 our resolution is sixteen bits, but the time constant of the low-pass filter that completes the digital to analog conversion will have to be 1/166 Hz × 65536 = 394 s if we are to capture our sixteen-bit resolution. With dac_step 8, our time constant need be only 1/1200 × 8192 = 6.8 s. The required time constant is inversely proportional to the square of dac_step. Our required resolution is 5 μm over a 5-mm range of motion, or 0.1%, which is 10 bits. Our required response time is of order one or two seconds. The time constant will be hard-wired on the circuit board with a capacitor. The dac_step and fck_divisor we can vary with commands.


Figure: Duty-Cycle DAC Properties. Resolution in bits, minimum time constant to provide the resolution.

Our software increments the DAC values at 200 Hz, incrementing ND, SD, ED, and WD by 1, 8, 64, and 512 counts respectively on each step. The duty cycle increases from 0% to 100 % in 328 s, 41 s, 5 s, and 0.6 s respectively. We have DCK on TP3. Current consumption is 610 μA from 1V2 and 160 μA from 2V5. We have 2V5 = 2.5 V during operation and 2.0 V during programming. Total power dissipation of the logic is 1.1 mW.

[23-SEP-22] We add logic chips to our two fully-assembled A3045As. All other parts were loaded onto paste and reflowed in our oven. Photograph of top and bottom sides here.